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Espressif Systems /ESP32-S3 /RMT /CH0_TX_STATUS

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Interpret as CH0_TX_STATUS

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0MEM_RADDR_EX0APB_MEM_WADDR0STATE0 (MEM_EMPTY)MEM_EMPTY 0 (APB_MEM_WR_ERR)APB_MEM_WR_ERR

Description

Channel 0 status register

Fields

MEM_RADDR_EX

This register records the memory address offset when transmitter of CHANNEL%s is using the RAM.
APB_MEM_WADDR

This register records the memory address offset when writes RAM over APB bus.
STATE

This register records the FSM status of CHANNEL%s.
MEM_EMPTY

This status bit will be set when the data to be set is more than memory size and the wraparound mode is disabled.
APB_MEM_WR_ERR

This status bit will be set if the offset address out of memory size when writes via APB bus.

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data